1. Technical Field
The present invention relates to a frequency synthesizer.
2. Related Art
Frequency synthesizers, each of which has a phase locked loop (PLL) for locking a phase of a signal or a frequency locked loop (FLL) for locking a frequency of a signal, have been known.
U.S. Pat. No. 6,690,215 discloses a configuration of the FLL for minimizing periodic quantization noise called idle tone. In U.S. Pat. No. 6,690,215, a delta sigma modulation signal is obtained by inputting a clock signal, which is output from a voltage control oscillator, to a frequency delta sigma modulation section (FDSM). The delta sigma modulation signal is input to a comparing section. Then, by generating the idle tone included in the delta sigma modulation signal at the time of locking a frequency of the clock signal and the idle tone of the opposite phase and inputting the idle tones to the comparing section, the comparing section eliminates the idle tones included in the delta sigma modulation signal.
U.S. Pat. No. 7,592,874 discloses a configuration of the PLL capable of locking the phase and locking the frequency of the clock signal by using a free-run counter and an accumulator.
In the apparatuses according to U.S. Pat. Nos. 6,690,215 and 7,592,874 mentioned above, it is possible to reduce a time period necessary for locking the frequency or the phase of the clock signal.
However, in the apparatus described in U.S. Pat. No. 6,690,215, a clock signal is assumed on the basis of the output of the frequency of the clock signal at the time of locking, and the idle tone of the opposite phase is generated. However, there is no fluctuation in an amplitude and a frequency component of the idle tone of the opposite phase. Hence, the fluctuation in the amplitude and the frequency component of the idle tone included in the delta sigma modulation signal in a case where the clock signal fluctuates is not dealt with, and the idle tone included in the delta sigma modulation signal cannot be eliminated. That is, two independent idle tones appear in the output, and as a result, a problem arises in that the idle tones increase.
The apparatus described in U.S. Pat. No. 7,592,874 has the same problem as the apparatus described in U.S. Pat. No. 6,690,215 mentioned above, except that the phase of the clock signal can be locked.